TSV (Through Silicon Via) heater

Tue, 02 Jun 2026 06:22:15 +0800

Out on the 300mm line, TSV stacking falls apart the moment thermal uniformity starts to drift. A single degree Celsius of excursion during the photoresist bake will throw off the via profile, and the particle burst from thermal cycling can kill the whole lot. We built the TSV heater to take that uncertainty off the table. What makes it tick, technically We run a short-wave infrared element with a quartz-based thermal architecture, so the heat couples directly and fast—no hot spots. Across the wafer, steady-state uniformity stays within ±0.1°C, and repeatability from bake to bake holds at ±0.05°C. Ramp rates top 10°C/s with controlled overshoot, which keeps the thermal budget on stacked dielectrics intact. Chamber materials were chosen for ultra-low outgassing, and the heater assembly sits comfortably in Class 1–100 cleanrooms. Particle generation is tamed by laminar flow and sealed interfaces, keeping surface particle counts under 0.01 particles/cm² at the process surface. Why this matters in TSV integration The bake step is where critical dimensions and sidewall passivation get set. With this heater, the soft bake and hard bake windows stay stable, so photoresist profiles stay in spec run after run—millions of shots, no surprises. Yield climbs because via etch and fill become predictable, and line-down events drop thanks to 24/7 reliability. The fast thermal response and tight coupling also cut energy use, shaving cycle time and operating cost without ever trading away precision. The practical bits you need Installation demands precise alignment to the wafer plane and a dedicated, low-noise power supply. The fast ramp is tuned for standard photoresist stacks; if you’re running thick BCB or polyimide, you’ll need to adjust the ramp profile to avoid stress-induced delamination. Plan a short commissioning run to map your thermal load and lock the recipe in.

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TSV (Through Silicon Via) heater